The invention relates to oscillators, and more particularly to a free-running oscillator synchronized with an external asynchronous pulse.
Computer systems are required to work efficiently with data stores of different speeds within the same system. If a semiconductor data store is used, the characteristics of the dynamic storage devices require that data in the storage elements be refreshed periodically. If store refresh operations are accomplished internally of the data store, the response time of the store will vary, and, accordingly, fully synchronous operation of a data store and the system central processor is not practical or desirable. Nevertheless, data transfer between the two units must be synchronized. One means of effecting synchronization between asynchronously operating units of a computer system involves resynchronization or restarting of a clock signal source of one unit, for example a free-running oscillator forming a part of such unit, with a clock signal from another unit. However, clock synchronizing circuits using logic gates are particularly susceptible to logic race conditions inasmuch as the asynchronous clock signals of the various units of the system drift with respect to each other. Such logic race conditions can result in the generation of clock signals having pulse widths of insufficient duration for proper system operation.
Accordingly, it is an object of the invention to provide an improved synchronizing circuit for a free-running clock signal generator.
Another object of the invention is to provide an improved free-running clock signal generator having a digital logic circuit for synchronizing the generation of the clock signals with an asynchronous clock signal from an external source.
Another object of the invention is to provide an improved digital-logic clock signal synchronizing circuit which provides protection against logic race conditions.